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Cadence Design Systems Sigrity 2018.04 x64 集成3D設計與分析,大幅縮短PCB設計週期
全新3D Workbench解決方案橋接PCB設計與分析,實現PCB設計成本與性能的大幅優化

楷登電子(美國Cadence公司,NASDAQ: CDNS)今日宣佈發佈Cadence® Sigrity™ 2018版本,該版本包含最新的3D解決方案,幫助PCB設計團隊縮短設計週期的同時實現設計成本和性能的最優化。 獨有的3D設計及分析環境,完美集成了Sigrity工具與Cadence allegro®技術,較之於當前市場上依賴於第三方建模工具的產品,Sigrity™ 2018版本可提供效率更高、出錯率更低的解決方案,大幅度縮短設計週期的同時、降低設計失誤風險。 此外,全新的3D Workbench解決方案彌補了機械和電氣領域之間的隔閡,產品開發團隊自此能夠實現跨多板信號的快速精準分析。

x64 | Languages:English | 
Description:
Sigrity software for simulation and signal integrity in high-frequency circuits. With the advancement of digital processing technology, the need for faster processing has grown increasingly, Prdzashgrhayy that necessarily needs to work faster circuits with higher processing speeds and higher frequencies are located. By increasing the speed signals for accurate speed up the signals on routes that are mounted on boards PCB or boards laminated issues and new problems arises in the case of Field, gripped Engineers will be events such as interference, distortion and noise and signal integrity at high frequencies cause to be subject to threats.

To minimize these threats, compensate them and increase the quality of high-speed circuits, needs analysis and corrective actions that the software Allegro Sigrity it is convenient for us. The software combines technology with design, editing and routing IC and PCB coordinate Cadence® Allegro® enables advanced analysis of both pre-layout and post-layout provides for users.

The software is designed to examine various scenarios in the initial phases allows accurate design and redesign minimized. This software supports reading and writing directly on the PCB and IC design of Allego's database. Accurate simulator based on SPICE as well as built-solver for 2d and 3d extracts the user. The software also modeling the transistor-level input and output functions include power-aware IBIS 5.0 support.

Features and Applications Allegro Sigrity:
-Perform a wide range of SI analysis or Signal integrity (signal integrity)
-Early detection of design errors to increase success in the early phases
-Restrictions can be set quickly and accurately apply the basic processes
-Improve product performance through exploration and space solutions
-Evaluation of alternative topologies in infancy
-Production of S parameters of the topology and signal analysis in the form of parameter S
-Tables estimate interference designed to increase productivity
-Was approved after PCB design and IC design directly on boards
-Multiple evaluation and confirmation signals for different paths on silicon boards

   

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